Abstract Looping on test vectors is a widespread requirement in failure analysis of semiconductor devices. The start of the loop and the number of vectors in the loop can be of critical importance. Present-day vector memory architecture tends to impose restrictions on both due to test speed requirements. A new Vector Loop Transformation algorithm is introduced to remedy the tester constraints.

Abstract In order to educate students in a practical way, a test object for a lab course is created: shorts and opens in an electrical model of physical defects are injected to a net list of a 4-bit arithmetic logic unit and are implemented in a Xilinx CPLD 9572XL. The fails are electrically controllable and observable in verification and electrical hardware test. By using a Test Access Port (TAP), the fails are analyzed in terms of their root cause. The arithmetic logic unit is used as a key component for lab exercises that complement the test part of an Integrated Circuit System Design and Test course in the master program Electrical Engineering and Information Technology at the University of Applied Sciences in Rosenheim. The labs include an introduction to a HILEVEL Griffin III test system, creation of pin and test setup, the import of vector files from verification test benches, control of a scan test engine and analysis of scan test data.

Abstract Optical or light beam induced current (OBIC or LBIC) are well known techniques for the analysis of integrated circuits and the study of electrically active materials in material science. They are also natural methods for analysis of photovoltaic cells, as the photocurrent of a photovoltaic cell itself is measured. We present a new measurement setup including graphical user interface software which has been created in a student project by refurbishing a used CNC (Computer Numerical Control) milling machine. The technique is applied to the measurement of the short circuit current of a photovoltaic (PV) cell with dimensions of 154 × 154 mm2.

Abstract Soft defect localization (SDL) is a method of laser scanning microscopy that utilizes the changing pass/fail behavior of an integrated circuit under test and temperature influence. Historically the pass and fail states are evaluated by a tester that leads to long and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before. This new method speeds up significantly the turn-around time in the failure analysis (FA) process compared to knowledge based FA.

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

Abstract A functional fail of a DRAM is analyzed by using an analog output of the device as an input signal of a microscope. Local heating by an IR laser changes the pass/fail behavior and thus the analog output of the DRAM. Although the observed spots do not belong to the physical defect, they give a starting point for further electrical analysis leading to the root cause of the failure. The paper will present a case study on a state-of-the art DRAM device failing with a timing problem. Especially the test aspects as well as the setup for the temperature dependent localization will be described. Finally an interpretation of the results will be proposed.