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1-3 of 3
Mark W. Jenkins
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Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 148-152, October 28–November 1, 2018,
Abstract
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As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 164-170, November 5–9, 2017,
Abstract
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Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area > 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 321-327, November 12–16, 2006,
Abstract
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Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.