In this paper, we present the first prototype of a Scanning Time-Resolved Emission (STRE) system consisting of a high-sensitivity, low-noise, and low-jitter single-point Superconducting Single-Photon Detector (SSPD) combined with a specialized scanning head of a Laser Scanning Microscope (LSM). This idea was first proposed in late 2006 [1] but required the right combination of detector, customization, and collaboration with a tool vendor to get to fruition. It should be understood that this is still a prototype system under development and significant improvements in acquisition time, resolutions, and performance are expected in the near future. In this paper, we will also present the first preliminary results acquired using a test chip fabricated in 32 nm SOI.

Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

This paper describes novel concepts in equipment and measurement techniques that integrate optical electrical microscopy and scanning probe microscopy (SPM) capabilities into a single tool under the umbrella of optical nanoprobe electrical (ONE) microscopy. Optical imaging ONE microscopy permits non-destructive measurement capability that was lost more than a decade ago, when the early metal levels became electrically inaccessible to microprobers. SPM imaging techniques do not have sensitivity to many types of defects, and nanoprobing all of the transistors in an area pinpointed by optical electrical microscopy is often impractical. Thus, in many cases, ONE microscopy capability will permit analytical success instead of failure.

High performance source/drain (S/D) stress-memorization technology (SMT) has been previously demonstrated to enhance electron mobility in leading edge SRAM NMOS designs. Dislocations initiating from SMT induced stacking faults cause electrical fails in the device. Transmission electron microscopy (TEM) results show that these dislocations can be reduced by controlling certain processing steps following SMT processing.

Root cause analysis of frequency sensitive “soft” failures in SRAM arrays pose unusual challenges to the failure analyst. Conventional atomic force probe (AFP) DC measurements cannot reliably identify the failure source. The employment of tester based schmoo screening have been shown to correlate with AFP AC quantitative capacitance measurements for the first time. The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for localization has been previously described [1,2,3]. By exploiting the dC/dV component of the NCVS signal shown in Figure 1 and integrating this output, a quantitative capacitance versus voltage measurement can be demonstrated. This quantitative capacitance measurement identified a frequency sensitve horizontal pair failure (HPF) in the SRAM array. Subsequent process vintage analysis identified the source and eliminated these frequency sensitive HPF characterisics. Given the sensitive nature of these fails, conventional physical analysis methods of TEM EELS, and cross section scanning capacitance analysis were not successful in finding the root cause. This underlies a paradigm shift in failure analysis. Electrical measurements may be the only means to identify a process problem and follow-up process vintage analysis is required to solution the root cause.