Abstract Post silicon validation techniques on Integrated Circuits (IC) specifically FIB circuit editing require backside sample preparation done by local mold compound and silicon machining. Conventional methods such as Computer Numerically Controlled (CNC) machining and chemical etching preparation platforms are commonly used. This paper will investigate a simple alternative approach to local sample preparation by using micro-abrasive blasting. This approach will display its simple natured set-up along with extremely quick process duration.

Abstract Logic diagnosis is the process of isolating the source of observed errors in a defective circuit, so that a physical failure analysis can be performed to determine the root cause of such errors. In this paper, we propose a new “Effect-Cause” based intra-cell diagnosis approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing (CPT) here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.