Abstract This paper presents a new sample preparation process for front side access for die with organic dielectric layers that are encapsulated in plastic packages. The limitation of the standard failure analysis flow is firstly described, showing the damage caused by wet etching. Then, the decapsulation method combining laser ablation and plasma etching is presented. It is completed by the process optimization. The final process makes it possible to perform failure analysis on low-k/Cu technologies in plastic package either by the front side or by the backside of the die.

Abstract Defects localization from the IC’s backside using hot spot detection techniques is discussed. Simulations are used to validate the applicability of hot spot detection from the silicon backside and to determine the optimal experimental conditions. The effects of the dissipated power, the substrate thickness and the defect position relative to the chip area are studied. These simulations take into account the thermal dependence of the silicon thermal conductivity. Transient simulations are also performed to evaluate the effect of modulating the power on the backside temperature difference. Backside Liquid Crystal Microscopy as well as Infrared Thermography and Thermal Laser Stimulation results on defective ICs are presented.