This paper presents a user-defined fault model (UDFM) that accounts for silicon behaviors that cannot be explained using traditional stuck-at and transition delay fault models. The new model targets cell-internal faults but does not require time-intensive SPICE simulations because it operates at the logic level. As added benefit, error logs collected using UDFM patterns (instead of traditional models) can be used to generate diagnostic callouts with improved resolution. A workflow that effectively achieves this is presented in the paper along with three case studies that demonstrate the usefulness of the proposed method.

Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact physical location of the defect. The default technique for isolating the defect location for this type of device is to start with a plan view S/TEM lamellae. Once the defect is located in plan view, the lamellae can be converted to cross-section (if necessary) for further characterization. However, if the defect is not detectable in plan view S/TEM analysis, an alternative approach is to examine the device in cross-section along either the x- or y- axis. Once the defect is located in the initial cross-sectional lamellae, it can be converted to the orthogonal axis if the initial cross-sectional lamellae did not provide adequate information for characterization. However, in converting a cross-sectional lamellae to the orthogonal axis, the initial lamellae must be exceedingly thin due to the dimensions of devices on 1x nm FinFET technologies, else other structures on the sample can obscure the view in the S/TEM. This can lead to structural integrity (warping) issues for the converted lamellae. In this paper, a novel solution to the warping issue is presented.