This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time, the top region of the test specimens could be completely removed down through the expected number of layers, making it possible to resolve details throughout the entire sample, particularly in the middle region of the 3D NAND, using TEM cross-section analysis.

In this work, two analysis methods for word line (WL) defect localization in NAND flash memory array are presented. One is to use the Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) to analyze the device through backside, which has no risk of damage during sample preparation. Depending on the I-V characteristics of defects, different analysis tools can be applied. The second method is to analyze a device defect location that is hard to detect through backside analysis. The precise defect site can be localized by Electron Beam Induce Resistance Change (EBIRCH) [1,2], and the defect profile can be observed. The large memory array in NAND flash structure leads to the wide sample movement during EBIRCH analysis. The sub-stage movement function used successfully solves this problem.

Protection layers on double ex situ lift-out TEM specimens were investigate in this paper and two protection layer approaches for double INLO or double EXLO were introduced. The improved protection methods greatly decreased the damage layer on the top surface from 90 nm to 5 nm (or lower) during FIB milling. According to the property of different sample and its preliminary treatment in the FIB, we have the satisfactory approaches to be applied. Using this improved protection method, we demonstrate the structures within the TEM lamella can be observed without ion beam damage/implantation during FIB

A recently developed technique known as Electron Beam Induced Resistance Change (EBIRCH) equipped with a scanning electron microscope (SEM) utilizes a constant electron beam (e-beam) voltage across or current through the defect of interest and amplifies its resistance variation. In this study, EBIRCH is applied for a 3D NAND structure device fault isolation but suffered from nearby dielectric film deformation. The characterization of such dielectric deformation and the possible mechanisms of e-beam induced damage are discussed. As well, a threshold condition to avoid from triggering the occurrence of dielectric damage is presented for shallow defect analysis in EBIRCH application.