Abstract Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

Abstract This paper will cover some of the options available to manage the failure analysis process when it is capacity constrained. This paper will provide a method to model a failure analysis operations capacity to aid in the decision process of where the constraints are. Several examples of solutions to some typical constraints will be presented also.

Abstract This paper describes a novel approach for safe handling of the thinned die from the front; a technique that can also be successfully applied to preserve cracked die. The discussion provides details on the characteristics and processes involved in backside reconstruction, thinned die reconstruction, and front-side deprocessing of thinned die. The finished backside reconstruction sample was cross-sectioned for examination using a diamond saw. After 6 hours of bake, no cracking of the thinned die was observed. Front-side deprocessing was then applied to the backside reconstructed sample. The sample remains intact. The technique has proven to be easily applied and highly reliable, and provides a solution for front-side deprocessing for both high pin count ball grid arrays and flip chips.