This paper describes the application of 3D FIB-SEM tomography as a method for quantifying process variations across the die and across the wafer, as well as layout investigations. In this study, the analysis of results acquired by 3D FIB-SEM tomography were applied to a 64L 3D-NAND device where process induced variation in the high aspect ratio vertical memory channels is measured and to a double stack 3D-NAND architecture, which is comprised of two 32-layer stacks where eccentricity of the pillars was evaluated for layers in both upper and lower stacks. In addition, a partial layout of a 14nm logic device is investigated by this method, demonstrating the capabilities for structural verification, and structural overlay of elements from a 7nm logic device were also evaluated. The results demonstrate the value of 3D FIB-SEM tomography for physical confirmation of the structural layout, which can be applied towards device debug and reverse engineering.