Static random access memory (SRAM) can occupy up to 90% of the die surface in a microprocessor and is often laid out with even more aggressive design rules than logic circuitry, which makes it more prone to manufacturing defects and more sensitive to process variations. As a result, SRAM is often chosen to be the process qualification vehicle during technology development and the yield learning vehicle during product manufacturing. Consequently, fast and accurate analysis of SRAM failure is critical to success on many levels. In this paper, we present a defect identification method that combines design for test (DFT) features, direct bitcell access (DBA), and nondestructive fault isolation techniques. With examples and case studies, it is shown how the approach makes use of electrical failure analysis data to greatly reduce the cycle time of root cause identification in the early stages of new technology development.

This paper presents a fast and accurate method for identifying defects responsible for SRAM bitcell failures. The steps involved in the process include functional testing, current-voltage measurements, and defect classification based on electrical failure analysis data. The entire procedure takes less than two hours and works for both hard and soft defects as well as reliability failures. A case study is included in the paper to demonstrate the efficiency of the nondestructive technique.

This paper explains how embedded assist and timing control techniques are being used to improve soft defect screening in nanoscale static random access memory (SRAM). The electrical stress test method is evaluated on advanced FinFET devices. As test results show, resistive and parametric defects that are difficult if not impossible to detect using conventional techniques become visible with the aid of assist and timing control circuits.

Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.