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Hyuk Ju Ryu
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Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 241-247, October 31–November 4, 2021,
Abstract
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This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 1-5, November 15–19, 2020,
Abstract
PDF
With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 100-102, November 15–19, 2020,
Abstract
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On older semiconductor technology, electron-beam probing (EBP) for active voltage contrast and waveform on frontside metal lines was widely utilized. EBP is also being extended to include the well-known optical techniques such as signal mapping imaging (SMI) with the use of a lock-in amplifier in the signal chain and e-beam device perturbation. This paper highlights some of the achievements from an Intel in-house built e-beam tool on current technology nodes. The discussion covers the demonstration of fin and contact resolution on the current technology nodes by EBP and the analysis of the SRAM array with EBP and EBP of metal lines. By utilizing EBP, it has been demonstrated that logic state imaging, SMI, and waveform have significantly improved spatial resolution compared to the current optical fault isolation analogues.