Massively parallel test structures, based on looking for shorts between certain design elements in the SRAM cells, are becoming increasingly relied upon in yield characterization. The localization of electrical shorts in these structures has posed significant challenges in advanced technology nodes, due to the size, and design complexity. Several of the traditional methods (nanoprobing, OBIRCH, etc.) are shown to be inadequate to find defects in SRAM cells, either due to resolution, or time required. In recent years, the Electron Beam Induced Resistance Change (EBIRCH) technique has increasingly been utilized for failure analysis. Combining EBIRCH with other techniques, such as SEM based nanoprobing system and PVC, allows not only direct electrical characterization of suspicious bridging sites but also allows engineers to pinpoint the exact location of defects with SEM resolution. This paper will demonstrate the several cases where SRAM-like test structures provided extreme challenges, and EBIRCH was the key technique towards finding the fail. A node to node, node to wordline, and ground-ground contact fails are presented. A combination of EBIRCH with the more traditional techniques in advanced technology node is key to timely and accurate determination of shorting mechanisms in our test structures.

Semiconductor Test Site structures were analyzed using an EBIRCH (Electron Beam Induced Resistance CHange) system. Localization of a RX (active area) to PC (gate) short was achieved with resolution that surpassed that of OBIRCH (Optical Beam Induced Resistance CHange). A voltage breakdown test structure at Metal 1 was stressed in the system, giving isolation to the specific contact. A five-fin diode macro was examined, and it is believed that the electrically active diffusions were imaged as individual fins from Metal 1. A series of ring oscillator devices were examined in steady state condition, and careful consideration of the image supports a hypothesis that Seebeck effect, from heating material interfaces in an EBIRCH system, is the reason for the “dipoles” reported in earlier literature.

Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.