Although the physical limits of CMOS scaling should have been reached years ago, the process is still ongoing due to continuous improvements in material quality and analytical techniques. This paper describes one such technique, electron channeling contrast imaging (ECCI), explaining how it is used to analyze nanoscale features and defects. ECCI allows for fast, nondestructive characterization and has the potential for extremely low detection limits. The detection of low-level defects requires measurements over large areas (usually with the help of automation) to obtain statistically relevant data. For example, automated ECCI mapping routines have been shown to quantify crystal defect densities as low as 1 x 10 5 cm -2 in epitaxially grown Si 0.75 Ge 0.25 . The paper presents various methods to reduce measurement time without compromising sensitivity. It also explains how the mapping routine can be optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers.

As semiconductor devices continue to shrink, novel materials (e.g. (Si)Ge, III/V) are being tested and incorporated to boost device performance. Such materials are difficult to grow on Si wafers without forming crystalline defects due to lattice mismatch. Such defects can decrease or compromise device performance. For this reason, non-destructive, high throughput and reliable analytical techniques are required. In this paper Electron Channeling Contrast Imaging (ECCI), large area mapping and defect detection using deep learning are combined in an analytical workflow for the characterization of the defectivity of “beyond Silicon” materials. Such a workflow addresses the requirements for large areas 10 -4 cm 2 with defect density down to 10 4 cm -2 .