Abstract An investigation into a high resistance via problem during the development phase of an advanced 0.25µm CMOS ASIC process is presented. The electrical signature of the via problem was low yield on fully processed device wafers. Further testing revealed that the logic (cell-based) sections of the chip were functioning, however the 512K bit SRAM was consistently failing. Based on the failing bit pattern, the failure area was isolated to contact-via stacks in the cell. Advanced wafer level failure analysis techniques and equipment such as focused ion beam milling, precision cross-section, and planar polishing techniques were utilized to identify the layer that was failing. Analysis results indicated a thin foreign layer or void between the aluminum line and the cap barrier layer of the line. Placement of a via on this line resulted in a high resistance node and subsequent device failure. As a further verification of the electrical failing signature, SPICE simulation was run on the SRAM cell circuitry. Optimization of the metallization stack was performed through experiments which resulted in the elimination of the mechanism.

Abstract An investigation into latent CMOS device isolation failures during the process development phase of an advanced 0.35 μm CMOS ASIC process is presented. The failure mechanism manifested itself electrically during wafer sort as a non-typical Iddq distribution and subsequently resulted in large leakage failures during reliability stress testing experiments. Emission microscopy analysis on failing units revealed specific leakage sites in the CMOS SRAM core. Layer removal/SEM inspections revealed no physical anomalies in the emission area. Manual toggling of the RAM internal electrical nodes revealed that the leakage occurred through a parasitic field transistor (i.e. between two P+ diffusion islands gated by a polysilicon runner). Probing of test structures with similar layout features revealed that the diffusion isolation between the P+ diffusions was marginal, resulting in subthreshold field leakage. In addition, the subthreshold leakage current between the two diffusions on the test structures increased as a function of stress voltage and time - similar to the failing signature of the actual SRAM. The mechanism responsible for the latent increase in leakage current is believed to be electron trapping near the drain end of the parasitic field device. Improvement of the transistor isolation properties was achieved through process modifications and subsequently the failure mechanism was eliminated

Abstract Optimization of the passivation scheme for a 0.35 μm TLM process is presented. The passivation layer is required to provide mechanical and chemical protection during the assembly and packaging process and long term environmental protection. The passivation scheme was optimized by testing a product-like test vehicle at accelerated environmental stress conditions of high humidity and high temperature. The initial passivation scheme showed a unique electrical test signature - a voltage dependent failure with open circuit at low voltage/pass at high voltage. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the failure site. Further cross-section analysis revealed that the failure site was a fracture across a via and adjoining IMO. This cracking was attributed to stress corrosion fracture of the IMO based on root cause analysis. This hypothesis required a path for moisture to the stressed IMO-2 location to cause the fracture. The moisture path was identified by further analysis and process changes to eliminate this were implemented. All subsequent parts passed the accelerated environmental tests confirming the stress corrosion fracture hypothesis.

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.