Abstract Pin-point (specific area) planar transmission electron microscopy (TEM) analysis has been improved to study process-induced defects in recent very large scale integrated (VLSI) devices. The specimens are prepared by a combination of marking failure sites with focused ion beam (FTB) equipment and planar TEM specimen preparation technique. This method provides not only planar observation of localized failures with an accurate observation with high positioning accuracy but also wide range of observable area which is feasible to carry out some application techniques associated with TEM. In particular, it is found to be a powerful method to identify the nature of crystalline defects which cause the failures. This work presents the detailed procedure and demonstrates its successful applicability via studying a leaky bipolar transistor in 0.5μm BiCMOS devices (one failure of more than 4500 transistors). The results clarify the presence of stacking faults, formed during epitaxial growth, between collector and emitter regions in the specific transistor with resistive collector-emitter leakage current.