Abstract A major failure mode known as ROMBIST (logic and memory) that topped the yield loss pareto and plagued a 0.13 m technology chipset production was analyzed. This MCUROM fail exhibited a unique failing pattern where every 4th row failed. A detailed electrical microprobing analysis had led to an exact model that was able to explain the failure mechanism. This model pinpointed a PFET extension implant blockage. Subsequent silicon etch analysis directed by the model prediction brought out the non visual defect (NVD). Inline inspection at the extension implant photo step identified the root cause. A greater than 45% reduction in die cost was realized in lots with photo resist fixes implemented.