With manufacturers now capable of creating transistors in the 5-7 nm node range, the ability to isolate, inspect, and probe individual metal and via layers is of the utmost importance for defect inspection and design validation. These isolated layers can be inspected for defects via SEM, provide design validation, or tested with electrical probing for failure analysis. The work herein describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using plasma focused ion beam (FIB) technology. The workflow is scalable and can be used in both lab and fabrication environments.

The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis, involving a critical etch step with aspect ratios of ~50:1. These high aspect ratio process steps present both fabrication and metrology challenges where the channel holes can bend, bow, and pinch off throughout the stack. Work presented herein demonstrates the capability of an automated workflow developed using the Thermo Scientific™ Helios™ G4 HXe DualBeam™ platform. The workflow iteratively exposes desired layers within the NAND stack, collects high resolution SEM images, and performs metrology to enable statistical analysis of trends as a function of depth within the stack. Results will be presented from 3 sites in an automatically delayered 72-layer 3D NAND die. Automated SEM metrology was performed every 10 layers, capturing more than 6000 devices. Over 19000 measurements were made on imaged devices yielding assessment of statistically significant trends in the planar cell area, eccentricity, and position of the bits as a function of depth.