Abstract This paper introduces a simple and effective technique of backside de-processing procedure. This technique reduces time and steps by simple wet etching. The front-side deprocessing requires many steps, such as wet and dry etching and parallel lapping, and also backside de-processing requires mechanical grinding to thin down the silicon thickness before wet etching. This paper introduces an effective way by skipping mechanical grinding and by etching at high temperature in case of thin flip chip. The backside silicon images are presented and compared after de-processing with TMAH and KOH which commonly have been used for bulk silicon etchant. The results show uniform backside images without any damage or residue. This backside de-processing technique was applied in two case studies to facilitate failure analysis.

Abstract Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.