Embedded cache size has dramatically increased with the advent of Intel Hyper-Threading and Multi-Core Technology, making many of the existing cache test validation method less and less practical, if not obsolete. As a result, the effort to sustain and improve array test quality, which is ever so critical to achieve DPM goals, is becoming a formidable challenge. In this paper, we present a test content validation procedure through novel application of Laser Assisted Device Alteration (LADA), i.e. soft fault injection in state elements, which had proven itself in Itanium® 2 array test quality improvement. While the procedure was originally targeting cache test content, the underlying concept has been successfully deployed to expedite scan test content and fault isolation tool validation.