Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.

The trend to higher integration of electronic devices to include more functions into ever-smaller devices, such as mobile phones or tablet computers, drives the development of novel packaging technologies for semiconductor chips. One of the approaches to reduce packaging size and power consumption is to stack multiple silicon chips on top of each other. An alternative approach is the utilization of through-silicon vias (TSV) to connect multiple chips to each other. This paper provides a set of sample preparation and analysis techniques for the comprehensive analysis of TSVs in support of technology development and qualification. The toolset ranges from simple cross-section imaging of cleaved samples to the evaluation of wafer planarity at the end of the TSV process flow and to the more specific analysis of the stress field around TSVs. The results provide valuable insights for designers, integration engineers, and process engineers.

This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

As the feature size of semiconductor technology shrinks, cross-section metrology becomes more and more challenging. The generation of cross section metrology data is important for the introduction of new advanced integration schemes, rapid yield learning, and continuous process control for stable manufacturing. In this paper an automated way of TEM cross-section preparation by FIB is described to ensure fast cycle time for preparation and analysis. A dual column FIB/SEM system is used to prepare TEM samples from multiple locations of a 300 mm wafer batch. Subsequently, the TEM lamella is transferred to a grid using an ex-situ lift-out station. Two dedicated applications are shown, a Focus Exposure Matrix (FEM) on patterned photo resist and a process control case study on an etched poly-silicon transistor gate.

In this paper an experimental set-up is presented that allows the Scanning Electron Microscope (SEM) in-situ investigation of electromigration phenomena in fully embedded copper interconnect structures, both from a top-down and from a cross-sectional perspective. The condition that the interconnects under test are fully embedded during the in-situ experiment is achieved using a Focussed Ion Beam (FIB) preparation technique. A SEM is equipped with a custom-made heating stage. During the experiment the void formation, growth and agglomeration process can be observed. Post-mortem cross-section analysis after the interconnect failure reveals e.g. a relationship between the microstructure of the copper contact and the non-constant growth rate of the voids.