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E. Susanto
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Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 79-85, November 10–14, 2019,
Abstract
PDF
Post-fault isolation layout net trace and circuit analysis based on abnormal hotspots is a critical step because it directly impacts the outcome of failure analysis. In this work, we review current commercial net tracing solutions in terms of their strengths and drawbacks. As an enhancement, a new net methodology that enables automation and the capability to execute tracing beyond first-level transistors is introduced. This approach could potentially eliminate manual net tracing and significantly improves the overall failure analysis turnaround time.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 520-526, November 6–10, 2016,
Abstract
PDF
In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.