Analog components are still an important aspect of our society's electronic portfolio. They play a role in the emerging and expanding 5G electronic industry, for instance. NPN bipolar junction transistors (BJTs) are the foundation of many analog circuits and have continually evolved to meet more demanding specifications. Certain embodiments of these NPNs, however, pose difficulties in failure analysis. Vertical NPN BJTs, with nanometer thick junctions extending several microns in length, are one such example. Although the high aspect ratio dimensions of these devices provide desired performance improvements, a subtle nanometer-scale defect anywhere along their length can cause electrical shifts detrimental to analog circuits. This paper examines the nature of these defects and explains how to isolate them using common failure analysis tools and special techniques.

Advanced packages such as 2.5D will continue to grow in demand as performance increases are needed in various applications. Failure analysis must adapt to the changes in the interfaces, materials and structures being developed and now utilized. Traditional techniques and tools used for selectively removing materials to isolate and analyze defects need to evolve alongside these packages. A CF4-free Microwave Induced Plasma (MIP) process is used to remove underfill (UF) with minimal alteration of other materials on the samples, a process which has become more difficult on 2.5D modules. UF is removed using this MIP process to allow subsequent analysis on interposer interconnects and ìbumps in crosssection. SEM inspection, Electron Beam Absorbed Current (EBAC), and FIB are techniques used post cross-sectional UF removal of these 2.5D structures. The benefits of the specific MIP process through case studies are presented. Specifically, the use of an automatic cleaning step and a CF4-free downstream O2 plasma allow easy removal of UF without damaging other structures of interest with little tool recipe development.

The limitations of Moore’s Law have led to alternatives in semiconductor packages that provide more functionality. Stacking multiple chips in 2.5D and 3D configurations has become a common solution. During the development of these technologies, test chains of chip to chip micro bumps and thru silicon via’s (TSV’s) at various regions within the stack are often employed. These present new challenges to the already difficult process of localizing open and resistive chain fails deep within the stack for root-cause analysis. A combination of quick and effective fault isolation techniques is often required to reliably isolate an open in a time critical situation. Capacitive measurements is a useful technique in some cases for obtaining a quick general location of an open. Magnetic Field Imaging (MFI), specifically Space Domain Reflectometry (SDR), is a non-destructive technique that can provide a relatively accurate location of an open. Electron Beam Absorbed Current (EBAC) is another useful technique in confirming and further isolating the open as the region of interest of the sample is approached via cross-sectioning or planar deprocessing. Case studies using these three techniques are presented and their strengths and weaknesses are discussed. The case studies focus on ìbump and chip bump chains in 2.5D samples.