Abstract Redistribution layer (RDL) bonding pad over active circuitry is utilized to re-route the original bond pad to other location for wire bonding using RDL. The damages in the active circuitry beneath the RDL bond pad induced by stress from wire bonding and package must be evaluated for reliability in the product development. The experimental approach and test structures are proposed in this paper. Functional fail was detected in electrical test after reliability tests on packaged IC. The dielectric cracking initiated by wire bonding that corresponds to the functional fail is identified by physical failure analysis and Transmission-Electron-Microscopy (TEM) at a specific location beneath the RDL bond pad. Finite element simulations are used to analyze the wire bonding stress distribution and circuit-under-pad design effect. The predicted maximum stress for the dielectric cracking matches to the location observed in the physical failure analysis. Based on the experiment and the simulation data, design rules for the circuit routing beneath the RDL bond pad have been successfully developed that all product reliability tests pass later with extend bonding power. The results lead to significant improvements in the robustness of circuit routing structure beneath the RDL bond pad for dielectric cracking without modifications of the existing processes for the product.

Abstract The single-bit charge loss of flash memory after stress has been investigated using TEM with selective chemical etching and TCAD simulation for the effect of silicon dopant profile and electrical failure analysis technique. However, the abnormal dopant profile on the drain-side of the failing bit observed in the TEM does not match the leakage behavior from the simulation. A qualitative model for the degradation process is proposed based on the electrical failure analysis results, it is suggested that the hole generated by avalanche breakdown captured by oxide traps on the drain-side during the stress is the source of leakage current.