Abstract The purpose of this paper is to present a systematic analysis methodology for a newly taped-out High Voltage (HV) product that has encountered a 0% yield issue. In order to identify the root cause and improve the yield, a series of electrical analysis experiments designed to reveal the failure phenomenon of the charge-pumping circuit were applied. Combining spice simulation data, I-V curve measurements, CAFM measurements and nano probing, the difference in resistance for a multi-fingered symmetric device was revealed. A deductive method was then used to conduct layout analysis, and an in-line split experiment was developed to explain the failure phenomenon experienced by the multi-fingered HV symmetric device for a charge-pumping circuit.

Abstract This paper presents a method of using a conductive atomic force microscope (C-AFM) to characterize a submicron metal fuse that has been blown open inadequately by laser. In order to obtain a proper I-V curve measured using the C-AFM without affecting the incompletely opened fuse, the paper proposes a method of preserving the fuse by coating its surface with spin-on glass. The paper explains how differences in laser cutting machines resulted in the high failure repair rate of customer product despite equivalent energy and spot size settings. Analysis of the fuse bank circuitry on wafers helped to find the critical physical differences between a fully blown and a poorly blown fuse. By overcoming difficulties in preserving the blown fuse failure sites for C-AFM measurement, laser settings could be easily optimized to ensure proper fuse opening.

Abstract Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.