Abstract The fabrication of semiconductor devices is handling, processing and test verification intensive all of which present opportunities for electrical over stress (EOS) or electro static discharge (ESD) to occur. Well-documented models for ESD exist. These include Human Body Model (HBM), Machine Model (MM) and Charged Body Model (CBM), but such is not the case for EOS and its manifestations. In addition, as device technologies change and reduce in dimension these geometric reductions create increases in operating currents and magnetic fields located on the die surface. When there are occasions where devices are overstressed electrically in new device technologies, the manifestation or evidence of the EOS maintains the same appearance while physical dimensions have become much reduced. On occasions, the manifestation or evidence of EOS in some new device technologies tends to appear different from anything we have seen in past device technologies. The resolution of these new failure modes is not trivial to analyze. This case study will detail the diagnostic journey used to resolve one such new and unique failure, the “Star Crack”.

Abstract This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.

Abstract Flip Chip packaging requires an understanding of the solder bump metallurgy and its aging characteristics. In this paper we demonstrate how standard failure analysis techniques can help determine aging characteristics and, how an understanding of bump age can be successfully employed to enhance bump reliability.