Abstract The semiconductor failure analyst’s tool box is a vast and resourceful set of capabilities that more than ever needs meaningful Memory Failure Signature Analysis (Memory FSA) as an important part of that suite. Today, this is driven by advanced process technology nodes that are producing virtually invisible defects to confound manufacturing and reliability. This demands greater attention to characterizing memory failures in order to theorize causes for failure and to implement suitable FA approaches and corrective action plans. Design Based FA (DBFA) techniques aim to extend this philosophy by focusing on a deep understanding of the chip’s Intellectual Property (IP), in terms of both content and architecture. It uses this knowledge to gain important insights into the behavior of the failure that otherwise may have been hidden or unobservable. This disciplined methodology leads to quicker closure for problems through implementing improved test screens, providing recommendations under a closed-loop Design for Manufacturing (DFM) system, enacting process enhancements, or some combination of all these areas. Here we present a clever technique to further aid in the failure signature analysis process and use it as an example for this Design Based FA methodology.

Abstract The advances made in process technology along with system-on-a-chip capabilities have made failure analysis ever more difficult and expensive to perform. Quick product time-to-market and the required high fabrication yields demand top quality performance from the failure analysis team. In this paper we present a methodology for embedded memory analysis (EMA) which provides design, layout, and process characterization, and yield and reliability enhancement for standard cell ASIC products. The methodology takes the power of memory testing and failure signature analysis and brings it to the logic chip to accurately predict root cause defects. We also present the application tool that is used to query, bitmap, analyze, and report the data, along with numerous case histories. This process has greatly improved failure analysis hit rates and provided much quicker turn-times for process improvement feedback and customer return root cause analysis.