Abstract Multi chip packages provide higher functionality in a module using multiplicity of dice. One specific packaging technology known as Stacked Chip-Scale Packaging raises new challenges for the failure analysis community. A methodology to perform full electrical isolation and failure analysis without damaging the electrical connectivity on either package or any of the dies in a stacked 2-die package is described. A second challenge is to obtain analysis result in a limited time frame in order to improve manufacturing yield and perform corrective action effectively. Example of successful failure analysis following this methodology on units with failure in packaging unit and units in failure in the die are presented.

Abstract This article outlines an optimal approach for board level CSP failure analysis, where the chip and printed circuit board are analyzed as a single unit to determine the root cause of the board level failures. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions, heating profiles or reflow, substrate warpage, and solder joint voids. This technique allows investigation of the above factors in a single sample preparation and readily arrive at the root cause solution in the minimum time. Results showed that package properties, the design of solder pads play the major role in determining how the fatigue behavior of solder joints will affect CSP component. Additional factors like nickel/gold and nickel palladium finishes were found to be more brittle and promote solder joint cracking.