Abstract This paper provides guidance and insights on the use of scanning capacitance microscopy (SCM) in semiconductor failure analysis. It explains why SCM systems are constrained by rigid performance tradeoffs and how CV measurements are affected by large stray capacitance and as well as edge effects associated with the 3D geometry of the sample and probe. It also explains how samples should be prepared and how proper sample preparation techniques combined with optimally selected voltages make it possible to accurately determine doping concentrations, even in p-n junctions.