The emergence of heterogenous integration driven by system-in-package (SiP) technology not only increases the complexity of semiconductor failure analysis, but also makes it more difficult to protect intellectual property because of the growing need to share design information to facilitate fault isolation in assembly and test. One way to address these challenges is through a computer-aided design (CAD) database that can be navigated across multiple components without exposing sensitive information. This paper describes the development and use of such a resource and how it enables safe and secure data sharing among supply chain partners.

In modern-day semiconductor failure analysis (FA), the need for computer-aided design (CAD) has extended beyond the sole physical layout to a much larger scope of integrated circuit (IC) design data, such as the source schematic and netlist. Due to the improved accuracy of predicted failures reported by test and diagnosis tools, it has become virtually mandatory to correlate the potential failing schematic features (e.g., nets and instances) to their corresponding location on the physical-CAD layout and actual device under test (DUT). This paper covers the latest advancements of utilizing IC design schematics for fast and accurate fault localization; along with some of the most-effective methodologies for efficient root-cause analysis.