As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.

Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.

Fluid ejection systems fabricated using MEMS (microelectromechanical systems) technology have a wide variety of applications ranging from ink jet thermal printing [1] to drug delivery for medical applications [2]. Microfluidic MEMS drop ejectors accurately control the volume and velocity of fluid dispensed. For the electrostatic drop ejector to function properly, the fluid must be contamination free, inert to the MEMS components and inert to materials and epoxies used for packaging. This paper will discuss the failure mechanisms and analysis techniques used to diagnose root cause(s) of failure in as-fabricated (unreleased) drop ejectors, and released, packaged drop ejectors tested in both air and water. Corrective actions implemented to mitigate the failure mechanisms and improve performance and reliability at both the wafer/die level and packaged level will be discussed.