Abstract A new analysis method using conventional emission microscopy (EMS) was developed for localizing open defects in CMOS LSIs. EMS is widely used for failure analysis of IDD (power supply current) leakage failures. The root cause of a failure is deduced by considering the emission characteristics associated with the IDD leakage current, emission shape, emission energy spectrum, and exact location on an Si die. Our new technique focuses on the observation of transient photoemission immediately after VDD application. During IDD leakage failure analysis, unique transient photoemission characteristics are observed. Immediately after VDD application, strong photoemission is briefly observed at the drain edge of an n-FET, but disappears after stabilization of the IDD current. We assumed that temporary photoemission would not be generated in transient behavior unless some kind of open defects were located at a specific conductor connected to the gate electrode. This mechanism was verified by nonbiased charge-up contrast of a conventional secondary electron image (SEI) and cross-sectional SEM observation at the defective open location. The dynamic method of observing transient photoemission proposed here is a very effective and practical way for detecting the locations of open failures in CMOS LSIs. Some examples of open mode failure analysis are described, along with cross-sectional TEM observations.

Abstract This paper describes a new technique, called the Light-Induced State Transition (LIST) method, that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows the user to locate a low signal line shortcircuited to a GND bus (or a high signal line shortcircuited to a VDD bus) in stand-by condition, which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by a experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS failure analysis, and has proved useful for finding a failure location rapidly.