Manufacturers of the emerging 3D NAND market are working to continually add more memory capacity by increasing the number of layers in the device stacks. As the device stacks get taller, the manufacturers face many challenges for creating the devices with very high aspect ratios (HAR)1 such as those shown in Figure 1. In order to monitor and improve the processes, metrology information is required for 3D analysis of critical dimensions and tilt/shift relative positions of the channels through the device height2.

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