As technology scales down, the density of Static Random Access Memory (SRAM) devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node. In addition, resistive defects and parametric defects are increasing which are hard to detect by the conventional test. Thus, the need of effective tests with high fault coverage and low cost increases. In this work, we study the reuse of assist technique (read and write assist) and timing margin control technique, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of hard-to-detect marginal defects. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits and timing control circuits can be leveraged to increase the defect coverage can be increases up to 28% at nominal operation voltage by simulation. Some successful case studies are also discussed to demonstrate the efficiency of the proposed electrical stress test methodology.