This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time, the top region of the test specimens could be completely removed down through the expected number of layers, making it possible to resolve details throughout the entire sample, particularly in the middle region of the 3D NAND, using TEM cross-section analysis.

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