Abstract
The occurrence of electrical overstress (EOS) failure in low-voltage core circuits resulting from latch-up test at the I/O pins was investigated, where a specific commercial IC product equipped with on-chip low-dropout regulator (LDO). Through failure analysis experiments, the root cause of EOS failures is identified to the abnormal LDO output voltage during latch-up test. In this work, a modified design featuring a deep n-well (DNW) beneath the NMOS region is proposed to mitigate EOS issue by enhancing electron absorption. Additionally, compensation network configurations are explored to explain the abnormal LDO operation. The experimental results from test chip have validated the effectiveness of the proposed modifications, emphasizing the importance of proactive measures in mitigating EOS failures.
