Abstract
Optical Fault Isolation (OFI) techniques have been still very effective method for semiconductor failure analysis such as silicon (Si) debugging and defect localization. Dynamic Laser Stimulation (DLS) is one of the most powerful application not only for marginal failure but also to isolate the potential design weak point at the early phase of product development. However, as circuit density of recent advanced system on chip (SoC) extremely increases with process scaling down, vector depth of products are also dramatically increased. This presents a challenging aspect for failure analysis because it is time consuming and reduces the accuracy of DLS analysis, which relies on test vector looping. As a consequence, it can lead to critical issues, such as missing the opportunity for design revision and slowing down the process improvement for yield enhancement This paper proposes a simple method of how to enhance the speed and accuracy of DLS evaluation for SCAN failure in high-density integrated circuits fabricated using the 3nm gate all around (GAA) process. Experimental results demonstrate that the proposed technique can reduce the time required for DLS analysis of SCAN failure while also increasing its accuracy.
