Abstract
In the field of semiconductor failure analysis, new sample preparation challenges arise due to the emergence of new chip architectures, such as 3D Back Side Imager (BSI) products. Indeed, these products are constituted of a specific stack: an imager chip at the top associated back-to-back with a digital chip at the bottom on a silicon substrate carrier. All the work presented hereafter is triggered by a nano-probing analysis case on a failing pixel of the imager chip. The analysis consists in characterizing the transistors of the pixel at contact level to isolate the electrical failure. It imposes to keep the integrity of the top chip (imager chip) front-end layers to have the possibility to measure the transistors. It can only be achieved by de-processing from the silicon substrate carrier side. Thus, the particularity of the 3D BSI chip conception implies a more complex delayering protocol than the ones commonly used. In this paper, the sample preparation protocol is presented in detail and its successful implementation is demonstrated through a concrete analysis case in 3D BSI 40 nm technology. This paper also discusses the advantages of the technical solutions implemented to overcome the complexity of the presented architecture.
