Abstract
Failure analysis for gate oxide breakdown is increasingly challenging as technology advances to smaller technology nodes. Previously, the cross-sectional passive voltage contrast (XPVC) technique has been successfully utilized in mature technology nodes to isolate gate oxide breakdown locations in complex polysilicon gate structures of planar transistors. However, as semiconductor technology advances, more intricate transistor structures such as FinFET are employed to improve device performance. This paper focuses on the application of the XPVC technique to metal gate structures and examines the challenges associated with its implementation in advanced technology nodes. We demonstrate the applicability of this method in 14nm FinFET devices in simulated gate oxide breakdown experiments showcasing successful sample preparation for subsequent Transmission Electron Microscopy (TEM) analysis.
