Non-planar semiconductor devices, such as vertical fin-based field-effect transistor (FinFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area. However, as circuits are scaled to smaller dimensions, it has become increasingly difficult to improve the performance of FinFET devices. Stacked nanosheet FETs have been developed to further enable larger effective conduction width in a given small layout area while enabling gate length scaling. Nanosheet (NS) FET devices have attracted attention as a candidate to replace FinFET technology at the 5 nm technology node and beyond due to their excellent electrostatics and short channel control. The use of silicon-germanium for the channel material has been explored as a major technology element for FinFET CMOS technology, and the performance benefits of Si-Ge channel over silicon channel have been demonstrated. Compared with conventional FinFET, stacked gate-all-around (GAA) NS CMOS shows higher electron mobility for nFET but lower hole mobility for pFET due to its unique device architecture and carrier transport direction. To improve pFET performance, SiGe NS is proposed as the pFET channel material. However, introducing and maintaining strain in the SiGe GAA NS channel is challenging but important for improving carrier transport. It is critical to understand the strain distribution in the advanced 3D nanosheet FET structures. This paper describes the use of advanced transmission electron microscopy (TEM) techniques to investigate the strain distribution in strained SiGe channel NS pFET through Si channel trimming and selective Si1-xGex epitaxial growth. A stacked GAA NS pFET was fabricated from compressively strained Si1-xGex channel with good crystallinity and high uniaxial compressive stress of ~1 GPa. From lattice deformation maps with a nanometer spatial resolution obtained by TEM techniques, the authors demonstrate that nano-beam precession electron diffraction techniques can be used to investigate the local strain distribution of the stacked GAA NS pFET devices with high precision, and thus help to optimize the integration process and strain engineering for pFET device performance enhancement for the next generation of CMOS logic in GAA NS technology.