This presentation provides an overview of chip-scale packages (CSPs) and the challenges they create for failure analysis. It begins with a review of stacked, multichip, and wafer-level packages, using images and illustrations to highlight complexities. It then presents examples of package-level failure mechanisms including various forms of cracking, inadvertent wire bond contact, and die-edge chipping. It likewise assesses die-level analysis challenges and provides practical solutions. The presentation also includes several case studies and describes new and emerging challenges.
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Issue Section:Package and Physical Analysis Challenges