Sub-nanometer fabrication processes and advanced packaging solutions such as 2.5D stacked silicon interconnect technology (SSIT) facilitate the production of high-performance ICs, but make physical failure analysis and debugging more difficult. For example, at 16nm, most diagnostic tools reach their limitations in terms of spatial resolution and signal sensitivity and require complex modifications and adjustments. In addition, a higher level of precision and uniformity is required for sample preparation. This paper describes a fault isolation technique that combines solid immersion lens (SIL) technology with precision die thinning. Two failure analysis case studies are presented to demonstrate the method, one a low level negative current leakage failure caused by ESD testing, the other a scan chain failure traced to the input of a delay buffer circuit. In both cases, success is attributed to the resolution and sensitivity of the SIL lens and the ability to precisely control die thickness.

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