Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

This paper explains how embedded assist and timing control techniques are being used to improve soft defect screening in nanoscale static random access memory (SRAM). The electrical stress test method is evaluated on advanced FinFET devices. As test results show, resistive and parametric defects that are difficult if not impossible to detect using conventional techniques become visible with the aid of assist and timing control circuits.