Fault Isolation using Layout Pattern Analysis

Many fabless customers do not share the design information such as LEF/DEF (Library Exchange Format and Design Exchange Format), design netlist, and test program information with foundries because they contain proprietary IP. Determining the root-cause of defects on such products only based on Sort test results and no scan diagnostics [1] for logic chips can be quite challenging. This paper presents a new layout pattern analysis methodology to isolate the failing weak layout structure using only the sort test results and the product GDS layout.