As scaling-down of dynamic random access memory (DRAM) has been continued, the pitch of metal-line already reached sub-50nm where it is hard to define the soft bridge and normal one. Moreover, the metal bridge failure at system level cannot be corrected with in-situ system error-code correction (ECC) modules. In order to screen these failures in the wafer or/and package level electrical tests, high voltage stress methods are necessary. Therefore, accurate stress quantity decided by combination temperature, voltage and time, and effective stress methodologies are essential for high quality and reliability. For a mass production environment, a wafer level burn-in (WBI) can enable multiple word-lines simultaneously and consistently is appropriate. Moreover, we confirmed the actual voltage level on real cells in WBI and optimized stress parameters in terms of time and voltage. Finally, it was proven through the WBI evaluation for over 60k DRAM chips.

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