As DRAM design rule (D/R) shrinks, the retention time due to leakage current becomes more important. Retention time failures that arise from gate induced drain leakage (GIDL) or junction leakage are exacerbated by changes in the electrostatic potential between adjacent lines or nodes. This study analyzes the effects of wordline (adjacent line) potential on retention time based on in sub-20nm DRAM technology. Electrical tests have confirmed that cells that fail from GIDL and junction leakage exhibit different behaviors according to the leakage characteristic and changes in adjacent wordline (especially in word-line across STI) potential. Simulations also confirm that these observations are due to the change in electric field. Based on these findings, a new perspective on the mechanism of retention failures is proposed.