Abstract

This paper presents an in-depth review of the critical front end stages of the fabricated integrated circuit (IC) assurance workflow used for recovering the design stack-up of a fabricated IC. In this work, a Serial Peripheral Interface (SPI) embedded on a 130 nm static random access memory (SRAM) chip is targeted for recovering the full design stack-up. This process leverages state-of-the-art techniques for high precision material processing and image acquisition to optimize and ensure the highest accuracy in the feature extraction stage. To this end, we present metrics that can be leveraged for optimizing the front end stages of the assurance workflow. Novel imaging figures of merit (FOM) for optimizing image acquisition parameters have been developed and are presented. The Image Quality Factor (IQF) FOM was established to quantify overall image quality as it pertains to feature extraction and the Quality and Efficiency Rating (QER) FOM was demonstrated to optimize imaging parameter selection, balancing image quality and image acquisition time.

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