Power consumption of conventional CMOS semiconductor architectures has grown to the point where novel structures need to be introduced to mitigate the power load within the chip. The introduction of the specialized artificial intelligence devices goes hand in hand with the inception of novel materials and processes into conventional semiconductor fabrication, which drives the need for expanding the host of failure analysis techniques and diagnostic capabilities. This paper describes a case study of elemental transmission electron microscopy tomography on an exploratory phase change memory test structure and comments upon some technique observations: advantages and disadvantages.

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