Abstract

The limitations of Moore’s Law have led to alternatives in semiconductor packages that provide more functionality. Stacking multiple chips in 2.5D and 3D configurations has become a common solution. During the development of these technologies, test chains of chip to chip micro bumps and thru silicon via’s (TSV’s) at various regions within the stack are often employed. These present new challenges to the already difficult process of localizing open and resistive chain fails deep within the stack for root-cause analysis. A combination of quick and effective fault isolation techniques is often required to reliably isolate an open in a time critical situation. Capacitive measurements is a useful technique in some cases for obtaining a quick general location of an open. Magnetic Field Imaging (MFI), specifically Space Domain Reflectometry (SDR), is a non-destructive technique that can provide a relatively accurate location of an open. Electron Beam Absorbed Current (EBAC) is another useful technique in confirming and further isolating the open as the region of interest of the sample is approached via cross-sectioning or planar deprocessing. Case studies using these three techniques are presented and their strengths and weaknesses are discussed. The case studies focus on ìbump and chip bump chains in 2.5D samples.

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