This paper presents Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) on a random time zero (t0) gate oxide defect within an IBM processor manufactured with a 14nm SOI (Silicon On Insulator) FinFET technology. The natures of the Functional Fail, the gate oxide defect, and the transistor characteristics are included.

The impact of this gate oxide defect to product yield and performance, plus the extent to which it extends across the product chip, which includes passing circuits, is covered. Since chips, which may contain this defect, could be present within the entire product lifecycle, the reliability aspects of the defect at the transistor level were investigated.

Among the various reliability stresses available for transistors, Constant Voltage Stress (CVS) Bias Temperature Instability (BTI) was chosen. CVS BTI stressing was able to be performed on both the NFETs and PFETs within the Inverter of the failing circuit, plus other identical reference circuits.

The BTI stress nanoprobing is covered. This includes an overview of BTI stressing, confirming the nanoprobing system and electrical stress/test programs are adequate for BTI stressing, BTI stress methodologies for Inverters, plus the BTI stress results.

The transistor level BTI stress results are discussed and compared to other published BTI literature. Finally, the reliability aspects of this gate oxide defect are discussed.

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