An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

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